im dying

4 files changed, 40 insertions, 43 deletions

diff --git a/report/report.aux b/report/report.aux
index a6d55d4..7be8ec5 100644
--- a/report/report.aux
+++ b/report/report.aux
@@ -1,3 +1,3 @@
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+\gdef \@abspage@last{10}
diff --git a/report/report.log b/report/report.log
index 709b23b..1a52bc1 100644
--- a/report/report.log
+++ b/report/report.log
@@ -1,4 +1,4 @@
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diff --git a/report/report.pdf b/report/report.pdf
index 0594044..69b779c 100644
--- a/report/report.pdf
+++ b/report/report.pdf
diff --git a/report/report.tex b/report/report.tex
index 700585f..afa7680 100644
--- a/report/report.tex
+++ b/report/report.tex
@@ -13,7 +13,6 @@
 
 \newcommand{\mathdefault}[1][]{}
 
-
 \geometry{
   a4paper,
   lmargin=1in,
@@ -23,8 +22,10 @@
 }
 \setlength{\droptitle}{-3em}   % This is your set screw
 
-
-
+\definecolor{codegreen}{rgb}{0,0.6,0}
+\definecolor{codegray}{rgb}{0.5,0.5,0.5}
+\definecolor{codepurple}{rgb}{0.58,0,0.82}
+\definecolor{backcolour}{rgb}{0.95,0.95,0.92}
 
 \title{\fontfamily{phv}\selectfont
 Analyzing Performance of Booth’s Algorithm and Modified Booth’s Algorithm}
@@ -72,7 +73,7 @@ Bit 2 & Bit 1 & Bit 0 & Action \\
 \bottomrule
 \end{tabular}
 \end{table}
-Because some operations require multiplying the multiplicand by 2, an extra bit is added to the most significant side of the workspace to avoid overflow. After each iteration, the result is arithmaticlly shifted right twice. The number of iterations is only half of the length of the operands. After all iterations, the workspace is shifted right once, and the second most significant bit is set to the first most significant bit as the result register does not include the extra bit.
+Because some operations require doubling the multiplicand, an extra bit is added to the most significant side of the workspace to avoid overflow. After each iteration, the result is arithmaticlly shifted right twice. The number of iterations is only half of the length of the operands. After all iterations, the workspace is shifted right once, and the second most significant bit is set to the first most significant bit as the result register does not include the extra bit.
 \par
 \section*{Simulation Implimentation}
 Both algorithims were simulated in Python in attempts to utalize its high level nature for rapid development. The table for Booth's algorithim was preformed with a simple if-then loop, while a switch case was used in modified booth's algorithim. Simple integers were used to represent registers. 
@@ -92,11 +93,8 @@ Hardware multipliers can help accellerate applications in which multiplication i
 % application should be considered
 % 
 
+\newpage
 \section*{Appendix}
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-\definecolor{codegray}{rgb}{0.5,0.5,0.5}
-\definecolor{codepurple}{rgb}{0.58,0,0.82}
-\definecolor{backcolour}{rgb}{0.95,0.95,0.92}
 
 \lstdefinestyle{mystyle}{
     backgroundcolor=\color{backcolour},
@@ -130,4 +128,3 @@ Hardware multipliers can help accellerate applications in which multiplication i
 \end{center}
     
 \end{document}
-